FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead

The existing implementations of the arbiter physical unclonable function (PUF) are based on synthesis of configurable symmetric paths, each link of which is a pair of two-input multiplexers providing two configurations of test signal translation: straight and exchange. To build a single link on FPGA, it is necessary to use two built-in LUT blocks, providing the implementation of two multiplexers, and the hardware resources of the LUT blocks are not fully utilized. The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family.