A CMOS low voltage, very low power fully differential orderly current buffer with ultra low input impedance and high CMRR

This paper presents the CMOS realization of the first generation orderly current buffer, OCBI. Its design is inspired by BJT version OCB. Employing CMOS technology leads to highly desired features of lower voltage operation, greatly lower power consumption and more economic integration compared to its BJT version. It has modular and fully differential structure in which a core cell is repeated as many times as required to provide the desired parameters. To practically study the performance of the block, it is simulated up to 3rd order. Pre and post-layout plus Monte Carlo simulations are performed under +/- 0.75V by Cadence using TSMC 0.18 mu m CMOS technology. Its performance is significantly improved especially in higher orders so that in Post-layout plus Monte Carlo simulations show the differential input impedance of 40.37 and 5.97, and the CMRR of 82.7dB and 102.1dB for the 1st and the 3rd order, respectively. This structure is greatly suitable for wide band applications by providing -3dB gain bandwidth in the range of 400MHz and wider. OCBI dissipates 365 mu W in 1st order and because of the added blocks, relatively more in higher orders. Corner cases simulation results are also provided indicating its well PVT insensitivity advantage.