List Scheduling in Embedded Systems under Memory Constraints

被引:0
|
作者
Arras, Paul-Antoine [1 ,2 ,3 ]
Fuin, Didier [2 ]
Jeannot, Emmanuel [1 ]
Stoutchinin, Arthur [2 ]
Thibault, Samuel [1 ,3 ]
机构
[1] Inria Bordeaux Sud Ouest, Talence, France
[2] STMicroelect, Grenoble, France
[3] Univ Bordeaux, Bordeaux, France
来源
2013 25TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD) | 2013年
关键词
Task graphs; scheduling; memory; system on chip; video decoding; ALGORITHMS;
D O I
10.1109/SBAC-PAD.2013.22
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through appropriate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20% can be achieved. Lastly, we show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics.
引用
收藏
页码:152 / 159
页数:8
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