The TH Express high performance interconnect networks

被引:46
作者
Pang, Zhengbin [1 ,2 ]
Xie, Min [2 ]
Zhang, Jun [2 ]
Zheng, Yi [2 ]
Wang, Guibin [2 ]
Dong, Dezun [1 ,2 ]
Suo, Guang [2 ]
机构
[1] Natl Univ Def Technol, Sci & Technol Parallel & Distributed Proc Lab, Changsha 410073, Hunan, Peoples R China
[2] Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China
基金
中国国家自然科学基金;
关键词
HPC; network interface chip (NIC); TH Express interconnect; offload collective operation;
D O I
10.1007/s11704-014-3500-9
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Interconnection network plays an important role in scalable high performance computer (HPC) systems. The TH Express-2 interconnect has been used in MilkyWay-2 system to provide high-bandwidth and low-latency interprocessor communications, and continuous efforts are devoted to the development of our proprietary interconnect. This paper describes the state-of-the-art of our proprietary interconnect, especially emphasizing on the design of network interface. Several key features are introduced, such as user-level communication, remote direct memory access, offload collective operation, and hardware reliable end-to-end communication, etc. The design of a low level message passing infrastructures and an upper message passing services are also proposed. The preliminary performance results demonstrate the efficiency of the TH interconnect interface.
引用
收藏
页码:357 / 366
页数:10
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