Evaluation of trench oxide protection techniques on ultra high voltage (10 kV) 4H-SiC UMOSFETs

被引：0

作者：

Rashid, SJ

Mihaila, A

Udrea, F

Malhan, RK

Amaratunga, G

机构：

[1] Univ Cambridge, Dept Engn, Cambridge CB2 1PZ, England

[2] Denso Corp, Res Labs, Aichi 4700111, Japan

来源：

SILICON CARBIDE AND RELATED MATERIALS 2003, PTS 1 AND 2 | 2004年 / 457-460卷

关键词：

SiC; trench MOSFETs; trench oxide protection; ultra-high voltage; UMOSFETs;

D O I：

10.4028/www.scientific.net/MSF.457-460.1441

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this study we have applied well known trench oxide protection techniques to UMOSFETs that are rated for 10kV as a means of reducing the oxide electric field at breakdown, thus improving oxide reliability in the device. The influence of a p(+) implant under the trench on device performance was investigated, and it was found that while this implant reduced the potential buildup in the trench oxide, the forward characteristics of the device were severely distorted. This was due to the occurrence of the JFET effect as well as quasi-saturation effects at high drain biases.

引用

页码：1441 / 1444

页数：4

共 8 条

[1]

AGARWAL AK, 1997, IEEE ELECT DEV LETT, V18

[2] TRENCH DMOS TRANSISTOR TECHNOLOGY FOR HIGH-CURRENT (100 A RANGE) SWITCHING [J].