All-Digital High-Resolution PWM With a Wide Duty-Cycle Range

被引：0

作者：

Morales, Juan I. ^{[1
]}

Chierchie, Fernando ^{[1
]}

Mandolesi, Pablo S. ^{[1
,2
]}

Paolini, Eduardo E. ^{[1
,2
]}

机构：

[1] UNS, CONICET, Dept Ing Elect & Comp, Inst Invest Ing Elect IIIE Alfredo Desages, Bahia Blanca, Buenos Aires, Argentina

[2] CIC Prov Buenos Aires, La Plata, Buenos Aires, Argentina

来源：

2019 ARGENTINE CONFERENCE ON ELECTRONICS (CAE) | 2019年

关键词：

Pulse-width modulation (PWM); delay-line; CMOS integrated circuits; high-resolution; programmable delay; DELAY-LINE;

D O I：

10.1109/cae.2019.8709295

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital high-resolution pulse-width modulator in standard 130-nm CMOS technology is presented in this work. The architecture is based on a digitally-controlled delay element with variable time interval up to 50 ps and adjustable against process, voltage and temperature (PVT) variations. Post-layout simulation results show a linear response between the control word and delay. The PWM modulator uses several delay elements in a hybrid configuration that allows to obtain duty cycles with 18-bit resolution, without using a high-frequency internal clock while maintaining low power consumption.

引用

页码：15 / 20

页数：6

共 16 条

[1] An evaluation and selection problems of OSS-LMS packages [J].

Abdullateef, Belal Najeh ;

Elias, Nur Fazidah ;

Mohamed, Hazura ;

Zaidan, A. A. ;

Zaidan, B. B. .

SPRINGERPLUS, 2016, 5 :1-35

[2] A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme [J].

Baronti, F ;

Lunardini, D ;

Roncella, R ;

Saletti, R .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (02) :384-387

[3]

Cho K, 2018, INT CONF ADV COMMUN, P585, DOI 10.23919/ICACT.2018.8323842

[4]

Dancy AP, 1997, IEEE POWER ELECTRON, P21, DOI 10.1109/PESC.1997.616620

[5]

Dehaene W, 2014, ANALOG CIRC SIG PROC, pVII

[6]

Gerasimov V. A., 2017, 2017 INT C IND ENG A, P1

[7]

Henzler S, 2010, SPR SER ADV MICROELE, V29, P1, DOI 10.1007/978-90-481-8628-0

[8] A digitally programmable delay element: Design and analysis [J].

Maymandi-Nejad, M ;

Sachdev, M .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (05) :871-878

[9] Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications [J].

Nakatani, Toshifumi ;

Rode, Jeremy ;

Kimball, Donald F. ;

Larson, Lawrence E. ;

Asbeck, Peter M. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (05) :1104-1112

[10] A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS [J].

Nuyts, Pieter A. J. ;

Singerl, Peter ;

Dielacher, Franz ;

Reynaert, Patrick ;

Dehaene, Wim .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (07) :1681-1692

← 1 2 →