Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology

被引：3

作者：

Marongiu, Andrea ^{[1
]}

Benini, Luca ^{[1
]}

Bartolini, Andrea ^{[1
]}

Acquaviva, Andrea ^{[2
]}

机构：

[1] Univ Bologna, I-40126 Bologna, Italy

[2] Univ Verona, I-37100 Verona, Italy

来源：

11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS | 2008年

关键词：

Leakage power; Energy management; Shutdown; DVFS;

D O I：

10.1109/DSD.2008.100

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Leakage power has become a major concern in nanometer technologies (65nm and beyond), and new strategies are being proposed to overcome the limitations of traditional dynamic voltage and frequency scaling (DVFS) and shutdown (SD) approaches in dealing with leakage power and with its strong dependency on temperature and process variations. Even though many researchers have proposed effective point-solutions to these issues, a detailed analysis of their impact on a commercial large-scale multimedia SoC platform is still missing. This paper presents an explorative and comparative analysis of DVFS and SD power management options on a multi-million-gate SoC in 65nm technology, and provides methodology directions and design insights.

引用

页码：259 / +

页数：2