Multiplexed Twin PLLs for Wide-Band FMCW Chirp Generation in 130-nm BiCMOS

被引：6

作者：

Ergintav, Arzu ^{[1
]}

Herzel, Frank ^{[1
]}

Fischer, Gunter ^{[1
]}

Kissinger, Dietmar ^{[2
]}

机构：

[1] IHP Leibniz Inst Innovat Mikroelekt, D-15236 Frankfurt, Oder, Germany

[2] Univ Ulm, Inst Elektron Bauelemente & Schaltungen, D-89081 Ulm, Germany

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2019年 / 29卷 / 07期

关键词：

Frequency modulated continuous wave (FMCW); frequency multiplexer (MUX); frequency synthesizer; radar; range resolution;

D O I：

10.1109/LMWC.2019.2916702

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a pair of fractional-N phase-locked loops (PLLs) followed by a multiplexer (MUX) integrated in one chip. The PLL outputs are multiplexed during chirp generation to increase the frequency modulated continuous wave (FMCW) signal bandwidth to 5GHz around a 31-GHz center frequency. The phase noise measured at the MUX output is -108 dBc/Hz at 1-MHz offset from a 31.07-GHz carrier. The chip occupies an area of 1.8 x 2.1 mm(2). The two PLLs together [excluding the voltage-controlled oscillators (VCOs)] draw 90mA from a 3.3-V supply, while the two VCOs, the MUX, and the output buffers draw 118 mA from 2.7 V. This array of PLLs offers a solution to improve resolution and precision of FMCW radar systems.

引用

页码：483 / 485

页数：3

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