Design and analysis of a jitter-tolerant digital delay-locked-loop based fraction-of-clock delay line

被引：3
|
作者：
Burnham, JR [1 ]
Yeh, GK [1 ]
Sun, E [1 ]
Yang, CKK [1 ]
机构：
[1] Stanford Univ, Stanford, CA 94305 USA
来源：
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS | 2004年 / 47卷
关键词：
D O I：
10.1109/ISSCC.2004.1332739
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：352 / 353
页数：2
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