According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as I-on, I-off, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.
