Zero Static-Power 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

被引：0

作者：

Liao, Chu-Feng ^{[1
]}

Hsu, Meng-Yin ^{[1
]}

Chih, Yue-Der ^{[2
]}

Chang, Jonathan ^{[2
]}

King, Ya-Chin ^{[1
]}

Lin, Chrong Jung ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Inst Elect Engn, Microelect Lab, Hsinchu, Taiwan

[2] Taiwan Semicond Mfg Co, Design Technol Div, Hsinchu, Taiwan

来源：

2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A full logic compatible 4T2R nonvolatile Static Random Access Memory (nv-SRAM) is successfully demonstrated in pure 40nm CMOS logic process. This non-volatile SRAM consists of two STI RRAMs embedded inside the 4T SRAM with minimal area penalty and full logic compatibility. Data is accessed through SRAM cells, and stored by switching one of the loading RRAMs by an unique self-inhibit feature. With this embedded STI RRAM storage nodes, data can be held under power-off mode with zero static power.

引用

页数：4