Impact of gate workfunction on device performance at the 50 nm technology node

被引：164

作者：

De, I ^{[1
]}

Johri, D ^{[1
]}

Srivastava, A ^{[1
]}

Osburn, CM ^{[1
]}

机构：

[1] N Carolina State Univ, Dept Elect Engn, Ctr Adv Elect Mat Proc, Raleigh, NC 27695 USA

来源：

SOLID-STATE ELECTRONICS | 2000年 / 44卷 / 06期

基金：

美国国家科学基金会;

关键词：

gate workfunction; super steep retrograde; channel engineering;

D O I：

10.1016/S0038-1101(99)00323-8

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operation. Classical device simulations suggest that the optimal workfunction is such that the gate Fermi level is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS) devices. However, when quantum mechanical effects are taken into account, the optimal workfunction is such that the gate Fermi level coincides with the conduction (valence) band edge. Midgap gates are not viable because the resulting short-channel effects are too severe. In a surrounding-gate transistor the optimal workfunction is attained when the gate Fermi level is 0.35 eV below (above) the conduction (valence) band edge in NMOS (PMOS) device. Midgap gates are not viable because the resulting threshold voltage is too high and cannot be reduced by lowering the substrate doping. (C) 2000 Published by Elsevier Science Ltd. All rights reserved.

引用

页码：1077 / 1080

页数：4

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