Bias Temperature Instability of Normally-Off GaN MIS-FET with Low-Pressure Chemical Vapor Deposition SiNx Gate Dielectric

In this work, characterizations are conducted to investigate the threshold voltage (V-TH) stability of the normally-off GaN metal-insulator-semiconductor (MIS-) field-effect transistor (FET) with fully recessed gate structure and highly reliable low-pressure chemical vapor deposition SiNx gate dielectric. We conducted bias-temperature instability (BTI) tests under both positive and negative gate bias. We demonstrated the highly stable V-TH of the high-performance MIS-FETs with small BTI, which benefits from the effective interfacial protection layer. More specifically, combining the BTI tests and drain current 1/f noise analysis, we present extensive investigation of the physical origins of BTI. According to the experimental evidence and analysis, we ascribe the V-TH instability to the trapping/detrapping of the pre-existing trap states located at the SiNx/GaN interface and/or in the gate dielectric.