Switched-Capacitor based Buck Converter Design using Current Limiter for better Efficiency and Output Ripple

被引：5

作者：

Das, Tamal ^{[1
]}

Mandal, Pradip ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India

来源：

22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/VLSI.Design.2009.43

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we are addressing power efficiency and output ripple of an embedded switched-capacitor based DC/DC Buck Converters. Here we propose to use current pump based switched-capacitor circuit in buck converter. The current pump circuit limits transition current of the switched-capacitors and hence, improves power efficiency and reduces output ripple. We have also proposed an equivalent macro model of this type of current pump based switched-capacitor converter which would help to get a better essence of the closed loop stability of the system and would reveal clearly trade-offs among load current, flying capacitance and clock frequency. A transistor level implementation of the proposed buck converter in 0.18 mu technology is provided. For a load current of 8mA (maximum) the achieved power efficiency is 72.7% and the output ripple is 27mV. The flying capacitors in the converter are 2x108pF and the load capacitor is 125pF.

引用

页码：181 / 186

页数：6