Analysis of 1/f noise in CMOS preamplifier with CDS circuit

Noise of CMOS charge sensitive preamplifier (CSA) and correlated-double sample and hold (CDS) circuit matching a capacitive source is calculated to analyze the relative portions of thermal and 1/f noise. In most radiation detector systems, PMOS transistor is used as an input transistor because of its lower 1/f noise than that of NMOS. But to study the 1/f noise reduction action of CDS circuit in the 1/f noise dominant condition, NMOS transistor is deliberately chosen as the input transistor of CSA. The theoretical minimum number of equivalent noise charge (ENC) that can be achieved in this system is about 1700 rms electrons for a 5pF detector capacitance. In order to demonstrate the theoretical analysis, a chip of CSA and CDS was designed in a 0.5 mum CMOS technology. The main amplifier is a differential input single-ended folded cascode and its measured gain bandwidth is over 5MHz. The measured ENC's of CSA-Shaper and CSA-CDS are 2105 and 3046 noise electrons, respectively.