共 50 条
- [1] Post-Silicon Validation of Yield-Aware Analog Circuit Synthesis 2019 16TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD 2019), 2019, : 245 - 248
- [2] A yield-aware modeling methodology for nano-scaled SRAM designs 2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, 2005, : 33 - 36
- [3] Yield-aware placement optimization 2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2007, : 1232 - +
- [4] Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning 2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 1244 - 1247
- [6] Variability-aware Parametric Yield Enhancement via Post-silicon Tuning of Hybrid Redundant MAC Units 2015 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2015,
- [7] Adaptive post-silicon tuning for analog circuits: Concept, analysis and optimization IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 450 - 457
- [8] Statistical Design and Optimization for Adaptive Post-silicon Tuning of MEMS Filters 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 176 - 181
- [9] Yield and Power Improvement Method by Post-Silicon Delay Tuning and Technology Mapping 2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2016, : 366 - 369
- [10] Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 464 - 469