A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

This paper describes three circuit technologies indispensable for high-bandwidth multibank DRAM's. 1) A clock generator based on a bidirectional delay (BDD) eliminates the output skew The BDD measures the cycle time as the quantity charged or discharged of an analog quantity, and replicates it in the next cycle. This achieves a 0.18-mm(2), two-cycle-lock clock generator operating from 25 to 167 MHz with a 30-ps resolution. 2) A quad-coupled receiver eliminates the internal skew caused by the difference between a rise input and a fall input by 40%, 3) An interbank shared redundancy scheme (ISR) with a variable unit redundancy (VUR) efficiently increases yield in multibank DRAM's. The ISR allows redundancy match circuits to be shared with two or more banks. The VUR allows the number of units replaced to be variable. These circuit technologies achieved a 250 Mb/s/pin, 8-bank, 1-Gb double-data-rate synchronous DRAM.