A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC

被引：18

作者：

Miro-Panades, Ivan ^{[1
]}

Beigne, Edith ^{[1
]}

Thonnart, Yvain ^{[1
]}

Alacoque, Laurent ^{[1
]}

Vivet, Pascal ^{[1
]}

Lesecq, Suzanne ^{[1
]}

Puschini, Diego ^{[1
]}

Molnos, Anca ^{[1
]}

Thabet, Farhat ^{[2
]}

Tain, Benoit ^{[2
]}

Ben Chehida, Karim ^{[2
]}

Engels, Sylvain ^{[3
]}

Wilson, Robin ^{[3
]}

Fuin, Didier ^{[4
]}

机构：

[1] CEA LETI DACLE, F-38054 Grenoble, France

[2] CEA LILST DACLE, Ctr Integrat Nanoinnov, F-91120 Palaiseau, France

[3] STMicroelectronics, F-38920 Crolles, France

[4] STMicroelectronics, F-38000 Grenoble, France

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 07期

关键词：

Adaptive voltage and frequency scaling (AVFS); chip multiprocessor; energy efficiency; globally asynchronous locally synchronous (GALS); ERROR-DETECTION; VOLTAGE; CMOS; IMPACT; DIE;

D O I：

10.1109/JSSC.2014.2317137

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independent voltage-frequency island. This architecture has been implemented on a 32 nm globally asynchronous locally-synchronous MPSoC. It shows up to 18.2% energy gains thanks to local adaptability compared with a global dynamic voltage and frequency scaling approach using 25% timing margins between slow and nominal process, by reducing margins to 60 ps of the real process. These gains are obtained for a total area overhead of 10% including local frequency/voltage actuators, sensors, and digital controller.

引用

页码：1475 / 1486

页数：12

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