4-BIT PIPELINE ADC FOR MONOLITHIC ACTIVE PIXEL SENSORS

被引：0

作者：

Agieb, Ramy Said ^{[1
]}

El Ghitany, Hassan Ahmed ^{[1
]}

Shehata, Khaled Ali ^{[1
]}

机构：

[1] Modern Univ Technol & Informat, Cairo, Egypt

来源：

PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER THEORY AND ENGINEERING (ICACTE 2009), VOLS 1 AND 2 | 2009年

关键词：

pipeline ADC; 1.5; bit/stage; digital error correction; bottom-plate switching;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Low voltage low power 4-bits 90Ms/s, 40 mu w, with DNL (+0.19/-0.4)LSB and INL (+0.47/-0.46)LSB is designed using 0.13um UMC CMOS technology operated with 1.2V voltage supply. The converter is composed of three stages the first, second stages produce 1.5bit/stage and last stage produce 2 bit/stage. Using Bottom-Plate Switching and fully digital error correction which corrects errors due to capacitor mismatch, charge injection, and comparator offsets. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles.

引用

页码：905 / 912

页数：8