High-speed hardware implementation of Gaussian normal basis inversion algorithm over F2m

In this paper a high-speed hardware structure for implementation of Itoh-Tsujii Inversion Algorithm (ITA) based on Gaussian normal basis hybrid-double multiplier is presented. To reduce the latency of the inversion operation, a hybrid-double multiplication with the number of clock cycles equal to a single multiplication is applied. Based on an efficient addition chain, double multiplication instead of single multiplication is used for implementation of inversion computations. In this case, two field multiplications are computed in parallel structure by hybriddouble multiplier. The proposed architecture is simple, low-cost and also the number of clock cycles in the structure are reduced compared to existing works. The proposed method over the binary finite fields F-2163 and F-2233 has been successfully verified and implemented on Virtex-4 XC4VLX100 and Virtex-5 XC5VLX110 FPGAs. The computation time of the structure on Virtex-5 FPGA family are 116.25 ns and 128.065 ns over two finite fields F-2163 and F-2233 respectively. The comparison results with other previous implementations of the inversion operation verify that the proposed method has better improvement in terms of execution time and performance.