Spider monkey optimization-based high-level synthesis in VLSI circuits for runtime adaptability

Very-large-scale integration (VLSI) is a procedure of designing integrated circuit (IC) by linking number of transistors into single chip where attaining the higher accuracy is difficult task because of variation in process-voltage-temperature (PVT). This work presents Stochastic Spider Monkey Optimization-based High-Level Synthesis (SSMO-HLS) Model to improve the performance with better runtime adaptability. In SSMO-HLS model, behavioral input is collected and dataflow analysis is carried out to convert input into dataflow diagram (DFD). Then, compilation process detects error functional unit (FU) in DFD. Spider monkey optimization is carried out to find optimal functional unit for performing allocation, scheduling, and binding process. After binding, output circuit gets generated with better runtime adaptability in case of PVT variations. The performance of SSMO-HLS model is carried out using ISCAS'89 Benchmark Dataset where designed model increases FU selection accuracy and reduces error rate and circuit adaptability time when compared to state-of-the-art works.