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- [31] A high speed word level finite field multiplier using reordered normal basis PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 3278 - 3281
- [37] Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation Journal of Computer Science and Technology, 2006, 21 : 887 - 892
- [40] On complexity of normal basis multiplier using modified Booth's algorithm PROCEEDINGS OF THE 7TH WSEAS INTERNATIONAL CONFERENCE ON APPLIED INFORMATICS AND COMMUNICATIONS, 2007, : 12 - 17