Single-Event Upset Prediction in SRAMs Account for On-Transistor Sensitive Volume

被引：12

作者：

Wang Tianqi ^{[1
]}

Xiao, Liyi ^{[1
]}

Huo, Mingxue ^{[2
]}

Zhou, Bin ^{[2
]}

Qi Chunhua ^{[1
]}

Liu Shanshan ^{[1
]}

Cao Xuebing ^{[1
]}

Zhang Rongsheng ^{[1
]}

Jing, Guo ^{[1
]}

机构：

[1] Harbin Inst Technol, Microelect Ctr, Harbin 150001, Peoples R China

[2] Harbin Inst Technol, Res Ctr Basic Space Sci, Harbin 150001, Peoples R China

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2015年 / 62卷 / 06期

关键词：

Monte Carlo simulations; single-event upset (SEU); soft error prediction; SRAM; TCAD; MULTIPLE CELL UPSET; CHARGE COLLECTION; CMOS TECHNOLOGY; HEAVY-IONS; NM CMOS; SIMULATIONS; DESIGN; IMPACT;

D O I：

10.1109/TNS.2015.2480880

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, single-event upset (SEU) is predicted using a combination of technology computer aided design (TCAD) and Geant4 Monte Carlo simulations. According to the layout topology of a 65 nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) arrays, the sensitive volumes (SVs) of off and on-transistors were calibrated by TCAD using novel circuit schematics. The effects of on-transistor charge collection on SEU were studied, and a novel criterion for SEU occurrence is proposed. Heavy ion simulation results indicate that the probability of SEU recovery increased with increased ion energy and striking tilt. The simulated SEU cross section and multiple cell upsets (MCUs) percentage based on the proposed method are in agreement with the experimental data for 6 T SRAM cells, which were fabricated using 65 nm processing technology.

引用

页码：3207 / 3215

页数：9

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