Depth profiling of border traps in MOSFET with high-k gate dielectric by charge-pumping technique

被引：25

作者：

Lu, Chun-Yuan ^{[1
]}

Chang-Liao, Kuei-Shu ^{[1
]}

Tsai, Ping-Hung ^{[1
]}

Wang, Tien-Ko ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 300, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2006年 / 27卷 / 10期

关键词：

border trap; bulk trap; charge pumped per cycle; charge-pumping (CP) technique; depth profile; high-k dielectric; interface-trap density;

D O I：

10.1109/LED.2006.882563

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (D-it). The charge pumped per cycle (Q,) versus high level (V-h) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Q p as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-k, gate dielectric/Si interface. The influence of border trap in high-k dielectric on the D-it measurement can be prevented by an appropriate selection of gate frequency in CP technique.

引用

页码：859 / 862

页数：4

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