Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

被引：5
|
作者：
Tokgoz, Korkut Kaan [1 ]
Kawai, Seitaro [1 ]
Okada, Kenichi [1 ]
Matsuzawa, Akira [1 ]
机构：
[1] Tokyo Inst Technol, Dept Phys Elect, Meguro Ward, 2-12-1-S3-27 Oookayama, Tokyo 1528552, Japan
来源：
IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 07期
关键词：
CMOS; mm-wave; MIMO; TX/RX switch; phased arrays; SPDT SWITCH;
D O I：
10.1587/elex.15.20180067
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 60 GHz antenna switching architecture is presented for millimeter-wave transceivers. This circuit topology re-uses the last stage's transistor of power amplifier (PA) and the first stage's transistor of low-noise amplifier (LNA) as switches, and the matching blocks. A two-stage LNA and a two-stage PA are designed considering antenna switching operation in 65 nm CMOS. The method has lower loss than conventional switches in receiver mode. The most important advantage is no additional area penalty compared to conventional methods. 2.9 dB minimum noise figure (NF) in the receiver mode is measured, and 2dBm of OP1dB is measured in the transmitter mode.
引用
收藏
页数：10
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