An optimization of bus interconnects pitch for Low-power and reliable bus encoding schemea

被引：0

作者：

Komatsu, Satoshi ^{[1
]}

Fujita, Masahiro ^{[1
]}

机构：

[1] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo, Japan

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Energy consumption is one of the most critical constraints in the current VLSI system designs. In addition, fault tolerance of VLSI systems is also one of the most important requirements in the current shrunk VLSI technologies. This paper presents low power and fault tolerant bus encoding methods considering coupling effects of bus interconnects. Experiments using SPEC2000 benchmark programs show that the proposed methods can effectively reduce signal transitions with fault tolerance. Moreover, the results show that the optimization of bus interconnects pitch can increase the effectiveness of the encoding method.

引用

页码：1723 / +

页数：2

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