Modeling and realisation of high accuracy, high speed current-steering CMOS D/A converters

This paper presents a closed design plan for high accuracy current steering D/A converters. All the steps in the design, from topology choice to the dimensioning of the D/A core, are covered, including the influence of random and systematic errors on the D/A converter's performance. Also, the necessity of a well considered layout is pointed out. To achieve the high accuracy performance, the matching properties become very important. Typically, the relation between matching and the D/A converter's INL yield is taken into account using CPU intensive Monte Carlo simulations. A new formula is statistically derived in this paper that describes, without any loss of design time, very accurately the impact of the matching on the INL yield and makes these Monte Carlo simulations superfluous. Furthermore, several measures are discussed to minimize the influence of the dynamic non linearities on the DIA converter's high frequency performance. Finally, the realisation and the measurement results of a 12 bit current steering D/A converter are presented. (C) 2000 Elsevier Science Ltd. All rights reserved.