共 50 条
[31]
Reliability evaluation of chip scale packages by FEA and microDAC
[J].
DESIGN & RELIABILITY OF SOLDERS AND SOLDER INTERCONNECTIONS,
1997,
:439-445
[32]
Reliability of chip scale packages under mechanical shock loading
[J].
56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS,
2006,
:584-+
[33]
Package-On-Package mechanical reliability characterization
[J].
2007 9TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2,
2007,
:557-570
[34]
Effect of EMC Properties on the Chip to Package Interaction (CPI) Reliability of Flip Chip Package
[J].
2017 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW),
2017,
:26-28
[35]
New generation wafer-level (chip scale) package technology delivers higher levels of power and reliability performance for power MOSFET devices
[J].
2003 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS,
2003, 5288
:327-332
[36]
Flip-Chip Chip Scale Package (FCCSP) Process Characterization and Reliability of Coreless Thin Package with 7nm Si Technology
[J].
IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022),
2022,
:266-270
[37]
Lead-free wafer level-chip scale package: Assembly and reliability
[J].
52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS,
2002,
:1355-1358
[38]
A parametric solder joint reliability model for wafer level-chip scale package
[J].
52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS,
2002,
:1323-1328
[39]
The influence of the chip-scale-package on the functioning and reliability of RF-MEMS switches
[J].
ICEPT: 2006 7TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS,
2006,
:626-+
[40]
CHIP SCALE PACKAGE - A LIGHTLY DRESSED LSI CHIP
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A,
1995, 18 (03)
:451-457