Low-swing on-chip signaling techniques: Effectiveness and robustness

被引:162
作者
Zhang, H [1 ]
George, V [1 ]
Rabaey, JM [1 ]
机构
[1] Univ Calif Berkeley, Dept EECS, Berkeley Wireless Res Ctr, Berkeley, CA 94704 USA
关键词
digital CMOS; low-power design; low-voltage; performance tradeoffs; reliability; special low-power 99;
D O I
10.1109/92.845893
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper reviews a number of low-swing on-chip interconnect schemes and presents a thorough analysis of their effectiveness and limitations, especially on energy efficiency and signal integrity, In addition, several new interface circuits presenting even more energy savings and better reliability are proposed. Some of these circuits not only reduce the interconnect swing, but also use very low supply voltages so as to obtain quadratic energy savings. The performance of each of the presented circuits is thoroughly examined using simulation on a benchmark interconnect circuit. Significant energy savings up to a factor of six have been observed.
引用
收藏
页码:264 / 272
页数:9
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