Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High-k Stacks

被引：57

作者：

Kerber, Andreas

Krishnan, Siddarth A. ^{[1
]}

Cartier, Eduard Albert ^{[2
]}

机构：

[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA

[2] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 12期

关键词：

Bias temperature instability; high-k dielectrics; metal gate; negative-bias temperature instability (NBTI); positive-bias temperature instability (PBTI); CMOS DEVICES; GATE; TECHNOLOGY;

D O I：

10.1109/LED.2009.2032790

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel voltage-ramp-stress (VRS) methodology is introduced for bias temperature instability testing of metal-gate/high-k (MG/HK) CMOS devices. Results from VRS are compared with the constant-voltage-stress procedure. It is demonstrated that the voltage and time dependence measured with both methods agree well with each other. These findings make the VRS test the preferred procedure for screening and process monitoring of MG/HK CMOS technologies because the test always yields measurable shifts and little knowledge about gate-stack details is required.

引用

页码：1347 / 1349

页数：3

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