Implications of proximity effects for analog design

被引：58

作者：

Drennan, P. G. ^{[1
]}

Kniffin, M. L. ^{[1
]}

Locascio, D. R. ^{[1
]}

机构：

[1] Freescale Semicond Inc, Tempe, AZ 85284 USA

来源：

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

10.1109/CICC.2006.320869

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper addresses two significant proximity effects, well proximity and STI stress, as they relate to analog circuit design. Device performance is impacted by layout features located near, but not part of the device. This adds new complexities to analog design. In either case, bias points can shift by 20-30%, causing potentially catastrophic failures in circuits. We show, for the first time, that a MOSFET placed close to a well-edge creates a graded channel.

引用

页码：169 / 176

页数：8

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