Parallel-Prefix Ling Structures for Modulo 2n-1 Addition

被引：14

作者：

Chen, Jun ^{[1
]}

Stine, James. E. ^{[1
]}

机构：

[1] Oklahoma State Univ, Dept Elect & Comp Engn, Stillwater, OK 74078 USA

来源：

2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS | 2009年

关键词：

computer arithmetic; adders; modulo addition; IMPLEMENTATION;

D O I：

10.1109/ASAP.2009.43

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Parallel-prefix adders draw significant amounts of attention within general-purpose and application-specific architectures because of their logarithmic delay and efficient implementation in VLSI. This paper proposes a scheme to enhance parallel-prefix adders for modulo 2(n) - 1 addition by incorporating Ling equations into parallel-prefix structures. As opposed to previous research, this work clarifies the use of Ling equations for Modulo and provides enhancements to its implementation. Results are given in this work for a placed and routed design within a variation-aware 45nm technology. The implementation results show a significant improvement in delay and even a reduction in power dissipation.

引用

页码：16 / 23

页数：8

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