A low-power dynamic ternary full adder using carbon nanotube field-effect transistors

Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are required for the same information transfer. Carbon Nanotube transistors (CNFETs) have many advantages over Metal Oxide Semiconductor transistors (MOSFETs), such as equal mobility of electrons and holes, the ability to adjust the threshold voltage by changing the nanotube's diameter, and lower leakage power. In this paper, a dynamic ternary full adder is presented using CNFETs. Subsequently, a 5-trit ripple carry adder is designed based on the proposed dynamic ternary full adder and buffer circuits. The proposed hybrid circuits are designed using clocked dynamic logic. Synopsys HSPICE simulator and Stanford's 32-nanometer CNFET model are used to simulate the circuits. The performance of the approach is evaluated under different supply voltages, loads, and temperatures. It is shown that the proposed full adder has lower power consumption, transistor count, PDP, and EDP compared with previously presented ternary adders. Furthermore, the proposed circuit is more robust to process variations.