Evaluation of layered tunnel barrier charge trapping devices for embedded non-volatile memories

被引：5

作者：

Boutchich, M. ^{[1
]}

Golubovic, D. S. ^{[1
]}

Akil, N. ^{[1
]}

van Duuren, M. ^{[1
]}

机构：

[1] NXP TSMC Res Ctr, B-3001 Louvain, Belgium

来源：

MICROELECTRONIC ENGINEERING | 2010年 / 87卷 / 01期

关键词：

Charge-trapping memory device; Data retention; ONO; High-k; Metal gate; Band gap engineering; Non-volatile memory; Flash; EEPROM; Reliability;

D O I：

10.1016/j.mee.2009.05.019

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents experimental results on band gap engineered charge trapping devices for embedded non-volatile memories. Different material systems with high-k dielectrics and metal gates were fabricated using 193 nm lithography and the electrical evaluation was performed on 256 bits mini-arrays. The structure relies essentially on a layered tunnel ONO (oxide-nitride-oxide) barrier that replaces the tunnel oxide in conventional SONOS devices. In addition, we have implemented high-k dielectrics, metal gates and sealing layer in order to achieve low programming voltage and improve the data retention especially at elevated temperature. Whereas, high-k and metal gate systems allow low programme/erase voltages attractive for embedded non-volatile memories, the conventional band gap engineered SONOS (BE-SONOS) offers better high-temperature data retention. However, compared to a SONOS device with a standard "thick" tunnel oxide of 6 nm close to the EOT of the layered tunnel ONO barrier, it appears that BE-SONOS memories suffer from charge loss toward the channel and therefore we believe that the band gap engineered feature of the ONO barrier requires alternative materials. (C) 2009 Elsevier B.V. All rights reserved.

引用

页码：41 / 46

页数：6

共 19 条

[1] Impact of annealing-induced compaction on electronic properties of atomic-layer-deposited Al2O3 [J].