Modified Low-Power Built-in Self-test for Image Processing Application

In recent trend, optimization of power without degradation of performance is major concern in application areas like embedded systems digital image and signal processing. The proper selection of test pattern/test image is one of the major issues. Ourmotivation of thiswork is to reduce the total power dissipation and area overhead of a Test pattern generator. The proposed BIST uses Negative Edge triggered D-Flip flop (NEDFF) for random pattern generation. When compared to existing LFSR with regular D-FF, our Modified LFSR with NEDFF reduces the count of transistors extensively. BIST using NEDFF is implemented and simulated using Microwind tool with 90 nm technology. The result reveals that significant amount of total power consumption is reduced while testing a VLSI circuit with NEDFF.