EFFICIENT FPGA EMULATION OF QUANTUM FOURIER TRANSFORM

被引：2

作者：

Qian, Yu ^{[1
]}

Wang, Mingyu ^{[1
]}

Chen, Jialin ^{[1
]}

Wang, Lingli ^{[1
]}

Feng, Zhihua ^{[2
]}

机构：

[1] Fudan Univ, Sch Microelect, Shanghai 200433, Peoples R China

[2] Beijing Inst Comp Technol & Applicat, Beijing 100854, Peoples R China

来源：

2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC) | 2019年

关键词：

D O I：

10.1109/cstic.2019.8755730

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Quantum computation shows its great advantage on exponential speed-up for some complex algorithms. Compared to software simulation with sequential execution, hardware emulation based on Field Programmable Gate Array (FPGA) can help to realize the intrinsic quantum parallelism. Quantum Fourier Transform (QFT) is the core of several quantum algorithms like Shor's algorithm. This paper proposes a recursive decomposition of QFT-n, which can be emulated with a pipeline architecture based on Intel Stratix IV FPGA device. Although QFT-8 is much more complex than QFT-5, experimental results show that our QFT-8 architecture can reduces 91% DSP blocks and 76% combinational ALUTs at the cost of 11x registers compared with QFT-5 in [4] on average.

引用

页数：3

共 5 条

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Chen, Jialin
Wang, Lingli
Charbon, Edoardo
Wang, Bin
[J]. PHYSICAL REVIEW A, 2013, 88 (02):
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Khalid, AU
Zilic, Z
Radecka, K
[J]. IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, : 310 - 315
[4] Lee YH, 2014, INT SYMP INTEGR CIRC, P512, DOI 10.1109/ISICIR.2014.7029495
[5] SHOR PW, 1994, AN S FDN CO, P124

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