Packet Filtering for FPGA-Based Routing Accelerator

被引：0
|
作者：
Antos, David [1 ,2 ]
Rehak, Vojtech [1 ]
Holub, Petr [2 ,3 ]
机构：
[1] Masaryk Univ, Fac Informat, Bot 68A, Brno 60200, Czech Republic
[2] CESNET, zspo, Prague 16000, Czech Republic
[3] Masaryk Univ, Inst Comp Sci, Brno 60200, Czech Republic
来源：
CESNET CONFERENCE 2006: FIRST CESNET CONFERENCE ON ADVANCED COMMUNICATIONS AND GRIDS | 2006年
关键词：
Packet filtering; hardware accelerated routing; filtering rules transformation; filter decision diagrams; binary decision diagrams;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present a novel approach for Binary Decision Diagram based semantically extended representation of packet filters called Filter Decision Diagrams (FDD), used for efficient filter processing and lookup in a hardware accelerator that uses a lookup engine employing CAM and comparison instructions kept in SRAM. We present the most important operations for FDDs and also give some complexity estimate. We also analyze and compare expressing power of the most commonly available packet filters.
引用
收藏
页码：161 / 173
页数：13
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