Parallel FPGA implementation of the split and merge discrete wavelet transform

The discrete wavelet transform has become a highly effective tool in many signal processing and data compression applications. In fact, it is widely accepted that JPEG2000, with its wavelet based image-coding technology will become the universally accepted format for digital images - whether on the web, over wireless systems, in digital cameras, printers, faxes or remote sensors. Various hardware implementations of the DWT were proposed by researchers to reduce its complexity and enhance its performance. In this paper we present an efficient hardware implementation of the discrete wavelet transform suitable for deployment on a reconfigurable FPGA based platform. Our implementation is a novel architecture based on the lifting factorization of the wavelet filter banks that uses the Overlap-State algorithm. It minimizes, memory usage, computational complexity, and communication overhead associated with parallel implementations.