An Enhanced Fault-Tolerant Routing Algorithm for Mesh Network-on-Chip

被引:6
作者
Rezazadeh, Arshin [1 ]
Fathy, Mahmood [1 ]
Rahnavard, Gholamali [2 ]
机构
[1] Iran Univ Sci & Technol, Dept Comp Engn, Tehran, Iran
[2] Shahid Chamran Univ Ahvaz, Sch Comp Engn, Ahwaz, Iran
来源
2009 INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS, PROCEEDINGS | 2009年
关键词
Network-on-Chip; virtual channel; deterministic routing; wormhole switching; delay; fault-tolerant;
D O I
10.1109/ICESS.2009.89
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Fault-tolerant routing is the ability to survive failure of individual components and usually uses several virtual channels (VCs) to overcome faulty nodes or links. A well-known wormhole-switched routing algorithm for 2-D mesh interconnection network called f-cube3 uses three virtual channels to pass faulty regions, while only one virtual channel is used when a message does not encounter any fault. One of the integral stages of designing Network-on-C hips (NoCs) is the development of an efficient communication system in order to provide low latency networks. We have proposed a new fault-tolerant routing algorithm based on f-cube3 as a solution to reduce the delay of network packets which uses less number of VCs in comparison with f-cube3. Moreover, in this method we have improved the use of VCs per each physical link by reducing required channels to two. Furthermore, simulations of both f-cube3 and our algorithm based on same conditions have been presented.
引用
收藏
页码:505 / +
页数:3
相关论文
共 19 条
[1]  
Ali M, 2005, 17TH ICM 2005: 2005 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, P178
[2]   A power and performance model for network-on-chip architectures [J].
Banerjee, N ;
Vellanki, P ;
Chatha, KS .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :1250-1255
[3]  
Benini L., 2002, IEEE Computer, Vol, V35, No, P70
[4]   FAULT-TOLERANT WORMHOLE ROUTING ALGORITHMS FOR MESH NETWORKS [J].
BOPPANA, RV ;
CHALASANI, S .
IEEE TRANSACTIONS ON COMPUTERS, 1995, 44 (07) :848-864
[5]  
DALLY WJ, 1987, IEEE T COMPUT, V36, P547, DOI 10.1109/TC.1987.1676939
[6]  
Dally WJ, 2001, DES AUT CON, P684, DOI 10.1109/DAC.2001.935594
[7]  
Dally WJ., 2004, PRINCIPLES PRACTICES
[8]  
Dao BV, 1999, IEEE T PARALL DISTR, V10, P7, DOI 10.1109/71.744829
[9]  
Duato J., 2003, Interconnection networks
[10]  
Guerrier P., 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), P250, DOI 10.1109/DATE.2000.840047