Fabrication and electrical transport properties of CVD grown silicon carbide nanowires (SiC NWs) for field effect transistor

We demonstrate the fabrication and the electrical transport properties of single crystalline 3C silicon carbide nanowires (SiC NWs). The growth of SiC NWs was carried out in a chemical vapor deposition (CVD) furnace. Methyltrichlorosilane (MTS, CH3SiCl3) was chosen as a source precursor. SiC NWs had diameters of less than 100 nm and lengths of several mu m. For electrical transport measurements, as-gown SiC NWs were prepared on a highly doped silicon wafer, pre-patterned by a photo-lithography process, with a 400 nm thick SiO2 layer. Source and drain electrodes were defined by e-beam lithography (EBL). Prior to the metal deposition (Ti/Au : 40 nm/70 nm) by thermal evaporation, the native oxide on SiC NWs was removed by buffered HF. The estimated mobility of carriers is 15 cm(2)/(VS) for a source-drain voltage (V-SD) of 0.02 V. It is very low compared to that expected in bulk and/or thin film 3C-SiC. The electrical measurements from nanowire-based field effect transistor (FET) structures illustrate that SiC NWs are weak n-type semiconductor. We have also demonstrated a powerful technique, a standard UV photo-lithography process, for fabrication of SiC nanowires instead of using EBL process.