Ballistic to diffusive crossover in III-V nanowire transistors

In this paper, we examine the crossover between ballistic and diffusive transport in III-V nanowire transistors. We find that at lower drain voltages the ballistic-to-diffusive crossover occurs at channel lengths of approximately 2.3 nm at room temperature. However, when we increase the drain voltage, we find that the ballistic-to-diffusive crossover can be more than nine times as long at room temperature. As the temperature is decreased, we find that the initially the performance is not significantly improved. However, as the temperature approaches 100 K, the ballistic-to-diffusive crossover increases to longer channel lengths quite dramatically. When InAs, InSb, and InP nanowires are compared at room temperature, we find that InAs and InSb perform in a similar fashion each with ballistic regions in excess of 10 nm, but that InP has no significant ballistic regime. Finally, we simulate several 10-nm InAs trigate transistors and show that for dopants deeply buried in the source and drain the devices appear ballistic, but when dopants appear near the source-channel interface, significant reductions in performance occur.