Model Order Reduction of Commensurate Fractional-Order Systems Using Big Bang - Big Crunch Algorithm

被引:16
|
作者
Jain, Shivann [1 ]
Hote, Yogesh, V [1 ]
Saxena, Sahaj [2 ,3 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Roorkee 247667, Uttar Pradesh, India
[2] Thapar Inst Engn & Technol, Elect & Instrumentat Engn Dept, Patiala 147001, Punjab, India
[3] Tel Aviv Univ, Sch Elect Engn, IL-69978 Tel Aviv, Israel
关键词
Fractional-order system; H-infinity error; integral square error; optimization; reduced order systems; soft computing; OPTIMIZATION; CONVERTER;
D O I
10.1080/02564602.2019.1653232
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a soft computing based scheme is proposed for the model order reduction of single input-single output commensurate fractional-order (FO) systems. The fractional-order system is first converted into an integer order (IO) system. The reduced order model of the corresponding integer order system is then determined via big bang - big crunch (BBBC) optimization algorithm. Finally, the reduced IO transfer function is transferred back to its FO form through an inverse substitution. The proposed approach is substantiated by two numerical examples of different orders. The effectiveness of the technique is demonstrated by the comparison of two performance indices, i.e. integral square error (ISE) and error and the response characteristics in time and frequency domain with the existing techniques from the literature. It is revealed that the response of the proposed BBBC based reduced order model is much closer to that of the original higher-order system.
引用
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页码:453 / 464
页数:12
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