The Sources of Erase Voltage Variability in Split-Gate Flash Memory Cell Arrays

被引：0

作者：

Tkachev, Yuri ^{[1
]}

Walls, James A. ^{[2
]}

机构：

[1] Silicon Storage Technol Inc, San Jose, CA 95134 USA

[2] Microchip Technol Inc, Tempe, AZ USA

来源：

2016 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW) | 2016年

关键词：

Flash memory; floating gate; tunneling; capacitance; single-electron transfer;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We performed a comprehensive analysis of the voltage-to-erase (V-erase) distribution in split-gate flash memory cell arrays. It was shown that V-erase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratio and FG channel parameters, have a minor effect on V-erase variability.

引用

页码：8 / 12

页数：5

共 11 条

[1]

[Anonymous], VLSI S A

[2] Overerase phenomena: An insight into Flash memory reliability [J].

Chimenton, A ;

Pellati, P ;

Olivo, P .

PROCEEDINGS OF THE IEEE, 2003, 91 (04) :617-626

[3]

Keeney SN, 2008, IEEE PR SER POWER, P179

[4]

Kotov K., 2002, P NVM TECH S, P110

[5]

Nagumo T., 2009, P IEEE IEDM

[6]

Ong T.C., 1993, S VLSI, P63

[7]

Tkachev Y, 2004, 2004 NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM, PROCEEDINGS, P45

[8]

Tkachev Y, 2006, PROC EUR S-STATE DEV, P411

[9]

Tkachev Y, 2016, IEEE INT C MICROELEC, P110, DOI 10.1109/ICMTS.2016.7476186

[10]

Tkachev Y, 2015, INT INTEG REL WRKSP, P99, DOI 10.1109/IIRW.2015.7437077

← 1 2 →