A 54 MBPS (3,6)-regular FPGA LDPC decoder

被引：49

作者：

Zhang, T ^{[1
]}

Parhi, KK ^{[1
]}

机构：

[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA

来源：

2002 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS | 2002年

关键词：

Application specific integrated circuits; AWGN channels; Bit error rate; Design methodology; Field programmable gate arrays; Hardware; Iterative decoding; Parity check codes; Routing; Throughput;

D O I：

10.1109/SIPS.2002.1049697

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10(-6) at 2dB over AWGN channel.

引用

页码：127 / 132

页数：6

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