A Frequency Synthesizer for Mode-1 MB-OFDM UWB applications

被引：1

作者：

Chang, Jung-Yu ^{[1
]}

Fan, Che-Wei ^{[2
]}

Liu, Shen-Iuan ^{[2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10764, Taiwan

[2] Natl Taiwan Univ, Taipei, Taiwan

来源：

2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | 2009年

关键词：

DESIGN;

D O I：

10.1109/VDAT.2009.5158134

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A frequency synthesizer for Mode-1 MB-OFDM UWB applications is realized in 65nm CMOS. By using a delay-locked loop (DLL) and the proposed multiply-by-two circuit, the frequency synthesizer achieves the in-band spur of -40dBc for the three-band operation. The proposed multiply-by-2 circuit realizes the quadrature signals, and its input signals do not need the 50% duty cycle. A modified current-starving cell in a DLL is also proposed to reduce the supply noise sensitivity. The measured switching time from 3.342GHz to 4.488GHz is around 1.1ns. The area is 1.25x1.175mm(2) with pads and the power is 19.2mW for 1.2V supply.

引用

页码：219 / +

页数：2

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