Exact delay fault coverage in sequential logic under any delay fault model

被引：4

作者：

Kumar, Mahilchi Milir Vaseekar ^{[1
]}

Tragoudas, Spyros

Chakravarty, Sreejit

Jayabharathi, Rathish

机构：

[1] So Illinois Univ, Dept Elect & Comp Engn, Carbondale, IL 62901 USA

[2] Intel Corp, Santa Clara, CA 95052 USA

[3] Intel Corp, Folsom, CA 95630 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2006年 / 25卷 / 12期

关键词：

delay fault testing; fault grading; fault simulation;

D O I：

10.1109/TCAD.2006.882583

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel function-based method for error propagation is proposed for exact delay fault coverage, using a single rated clock for fault activation under any delay fault model. Sequential circuits without full scan are considered. A latched error at a flip-flop represents one or more delay faults and is allowed to propagate to an observable point with or without the support of other latched errors. Existing methods allow only one flip-flop to have an error during the propagation phase to simplify the process of error propagation at the expense of decreased fault coverage. The advantage of the proposed method is demonstrated experimentally using the path-delay-fault model with more than 20% improvement in fault coverage.

引用

页码：2954 / 2964

页数：11

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