CYCLONE: Automated design and layout of RF LC-oscillators

被引：48

作者：

De Ranter, CRC ^{[1
]}

Van der Plas, G ^{[1
]}

Steyaert, MSJ ^{[1
]}

Gielen, GGE ^{[1
]}

Sansen, WMC ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT, MICAS, Dept Elect Engn, B-3001 Louvain, Belgium

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2002年 / 21卷 / 10期

关键词：

D O I：

10.1109/TCAD.2002.802267

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.

引用

页码：1161 / 1170

页数：10

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