A New Integration Technology Platform: Integrated Fan-Out Wafer-Level-Packaging for Mobile Applications

被引：0

作者：

Yu, Douglas ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co R&D, 168 Pk Ave 2,Sci Based Ind Pk, Hsinchu, Taiwan

来源：

2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

3D sub-system integration of logic and DRAM with TSV is desirable for wide memory bandwidth and reduced power for mobile applications. However, its manufacturing cost, along with testing and heat dissipation, remains to be outstanding issues. A new integration technology platform, InFO, is proposed to address it. In this paper, we compare three main 3D integration architectures: InFO_PoP, FC_PoP and 3DIC with TSV based on mobile product requirements, including system power-performance-profile (form factor), heat dissipation, memory bandwidth and production cycle-time along with cost. InFO not only best optimizes and achieves the requirements, but also more readily integrates partitioned-chips, which further impacts on the manufacturing of the logic/DRAM sub-system.

引用

页数：2