An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times

被引：0

作者：

Chunn, Ankush ^{[1
]}

Agrawal, Akshay ^{[1
]}

Naugarhiya, Alok ^{[1
]}

机构：

[1] Natl Inst Technol Raipur, Dept Elect & Commun Engn, Raipur, Madhya Pradesh, India

来源：

2020 24TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT) | 2020年

关键词：

DTMOS; Subthreshold SRAM; low power; Transmission gate SRAM; LOW-POWER;

D O I：

10.1109/vdat50263.2020.9190442

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, an SRAM cell based on Dynamic threshold voltage MOSFET technique is analyzed for its performance in sub-threshold region. The cell utilizes a total number of 8 transistors with transmission gate based access transistors. Simulations are done on Cadence Virtuoso tool using 45nm GPDK in sub-threshold voltage regime. The proposed cell when compared with the conventional 6T SRAM cell shows 80% reduction in read access time, 63.95% reduction in write '1' access time and 22.7% reduction in write '0' access time. The proposed cell also shows 360% increase in Write static noise margin (WSNM). However, the power consumption is seen to increase by 400% during read operation, by 221.4% during write '0' operation and by 458.4% during write '1' operation.

引用

页数：6

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