Design and reliability of a new WL-CSP

A new wafer level package has been designed and fabricated in which the entire package can be constructed at the wafer level using batch processing. Peripheral bondpads are redistributed from the die periphery to an area array using a redistribution metal of sputtered aluminum or electroplated copper and a redistribution dielectric. Redistribution of metal at the wafer level aids in eliminating the use of an interposer, or substrate. The redistributed bondpads are plated with the underbump metallurgy and then bumped using solder ball placement. The solder balls are reflowed onto the wafer creating a large standoff that improves reliability. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 nun pitch of an 8 x 8 array of bumps on a 5 x 5 mm(2) die. The bump structure and package geometry have been optimized using simulation and validated by experimentation. The board used for reliability testing is a 1.2 mm thick, 2-layer FR-4 board with non-soldermask defined landpads with OSP (organic solderability preservative). The landpads are the same diameter as the redistributed bondpads. Package and board level reliability data will be presented.